1. Technical Field
This disclosure relates to integrated circuit design, and more particularly to a method for reconfiguring and modifying register transfer language code base.
2. Description of the Related Art
Integrated circuit design flow is a complex process. Most often, a functional/behavioral description of the system/circuit is created with use of a register transfer language (RTL) or hardware description language (HDL) such as Verilog or VHDL (Very high speed integrated circuits Hardware Description Language). An important part of the design process is the creation of a logic implementation, and subsequently a transistor level implementation of these behavioral models. The creation of these implementations is oftentimes automated through the use “synthesis” tools. Generally, a synthesis program is used to generate a netlist from the HDL models, making use of standard cell libraries containing a variety of circuit elements from which the integrated circuit may be constructed. Netlists usually include instances of the standard cells contained in the design, with the possible inclusion of custom blocks, and information descriptive of the connectivity between all the instances included in the integrated circuit. There are different types of netlists that can be used, including physical and logical netlists, instance-based and net-based netlists, and flat and hierarchical netlists. Typically, the final netlist generated by the synthesis tool is dependent on the constructs that appear in the HDL model. In other words, the style and syntax of various functional elements in the HDL oftentimes determines the type of elements and components that appear in the netlist generated by the synthesis tool.
Because the design cycle for integrated circuits is complex and there are many steps, integrated circuits may oftentimes include circuit blocks that are exchanged between designers and design engineers as completed blocks. Part of this process includes one group of engineers, e.g. working for Intellectual Property (IP) vendors, delivering RTL code bases representative of a given design to another group of engineers. However, RTL code bases tend to change over time as the IP vendors deliver RTL drops. When such drops occur, prior RTL edits for performance improvements need to be maintained. In other words, an RTL code base delivered by an IP vendor might be modified and improved by the engineers receiving the RTL code. However, subsequent RTL drops of updated versions of the same given design by the IP vendor will be missing the modifications and improvements that have been made for previous versions, as any such modifications and improvements will be the IP of the receiving engineering team. However, it is obviously desirable for the receiving engineering team to port the improvements from the previous version to the current version of the RTL code base. Existing techniques for dealing with this task involve reliance on manual merging/editing of code or reliance on synthesis time modifications, which tend to be inefficient and error-prone.